Can we create rules to stop Wall Street from ripping us off? No, says Wall Street. You aren’t smart enough to understand what we do. Your rules and regulators will just get stomped by traders. All your pathetic attempt to keep up with us will do is stifle innovation. So shut up and let the grownups do their thing.
Imagine if Apple said, you can’t write rules to protect you from your iPhone exploding or frying your brain. You aren’t smart enough. All you’ll do is stifle innovation. Would anyone take them seriously? Fuggedaboutit.
Is it because you understand how your iPhone’s physical innards work? For that matter, how the brakes on the last elevator you rode on works? Or the engines of the last jet you flew on? I’m guessing not.
Most of us are ignorant techno-peasants, swimming in a river of quasi-magical objects we don’t really understand. But that doesn’t mean we give manufacturers a free pass.
How do we do it? As a society, we’ve put together rules of the game that foster an ecosystem of players that create checks and balances and stack the deck in favor of us not getting killed and foster innovation. It’s not perfect, but it works.
Why should Wall Street’s “products” be treated any differently?
UPDATE: based on some feedback I got, some folks really don’t get how insanely complicated the iPhone is — they think derivatives are much, much harder to understand. So here’s a reality check. This is the least geeky explanation I could find of just one piece of the iPhone’s innards:
The CPU is based on the ARM11 core, in specific it is the ARM1176JZF-S. The CPU runs at 412MHz to save power, although the core is capable of running at 667MHz. The ARM11 CPU is a single-issue in-order microprocessor with an 8-stage integer pipeline. It’s got a 32KB L1 cache (16KB for instructions, 16KB for data) and no L2 cache. The ARM11 CPU in the iPhone also has a vector floating point unit, but thankfully the SoC includes a separate GPU for 3D acceleration….Paired with this CPU is a PowerVR MBX-Lite GPU core. This GPU, like the CPU, is built on a 90nm process and is quite simple. The GPU does support hardware transform and lighting but it’s fully fixed function, think of it as a DirectX 6/7 class GPU (Riva TNT2/GeForce 256).
Here’s PowerVR’s block diagram of the MBX:
The MBX-Lite in the iPhone shares the same architecture as the MBX but is optimized, once more, for power efficiency and thus is significantly slower.
Personally, I think comparing the iPhone’s GPU to a DirectX 6/7 class GPU is like comparing a Degas to a Kandinsky –- actually I don’t, because I have no freakin’ idea what they’re talking about. If they’d put this Kandinsky in place of the MBX’s block diagram, I wouldn’t have been any worse off. Although I get software, when it comes to hardware I’m more of an “iPhone pretty, Ogg Like iPhone” kinda guy.
And remember, kids, that iPhone hardwaregeeksprecken is just the tip of the iceburg. Just to make sense of that explanation, you need to know, for example, what a “vector floating point unit” is. Here’s the least geeky explanation I could find of what they mean by “vector” when they say “vector floating point unit”:
In general terms, CPUs are able to manipulate one or two pieces of data at a time. For instance, many CPUs have an instruction that essentially says “add A to B and put the result in C,” while others such as the MOS 6502 require two or three instructions to perform these types of operations.The data for A, B and C could be—in theory at least—encoded directly into the instruction. However things are rarely that simple. In general the data is rarely sent in raw form, and is instead “pointed to” by passing in an address to a memory location that holds the data. Decoding this address and getting the data out of the memory takes some time. As CPU speeds have increased, this memory latency has historically become a large impediment to performance.
In order to reduce the amount of time this takes, most modern CPUs use a technique known as instruction pipelining in which the instructions pass through several sub-units in turn. The first sub-unit reads the address and decodes it, the next “fetches” the values at those addresses, and the next does the math itself. With pipelining the “trick” is to start decoding the next instruction even before the first has left the CPU, in the fashion of an assembly line, so the address decoder is constantly in use. Any particular instruction takes the same amount of time to complete, a time known as the latency, but the CPU can process an entire batch of operations much faster than if it did so one at a time.
Vector processors take this concept one step further. Instead of pipelining just the instructions, they also pipeline the data itself.
Any questions?
